A Paper Vlsi

8D-2

Adiabatic CMOS Gate and Adiabatic Circuit Design for Low-Power Applications

Guoqiang Hang

Department of Information and Electronic Engineering

Zhejiang University, Hangzhou 3 10027, CHINA

Tel: +86-571-87952017

Fax: +86-571-8795 1709

E-mail: hanggq@mail.hz.zj.cn

Abstract- The methodology for designing adiabatic circuits

employing two-phase power clock, is investigated. First,

algebraic expressions for and properties of power-clocked

signals are discussed. Then the design of adiabatic gates based

on AC power supply and CMOS transmission gates is

analyzed. On this basis, basic rules for the design of adiabatic

circuits are proposed, and a design example of an adiabatic

full adder is demonstrated. SPICE simulations using a

trapezoidal power-clock demonstrate that the designed

adiabatic circuits have a correct logic function and ultra

low-power characteristics.

I. INTRODUCTION

Adiabatic computation has been widely studied as a

low-power design technique. In the recent years, several

adiabatic or energy recovery logic architectures have been

proposed[ 1-61. They have achieved significant power

savings compared to conventional CMOS circuits. The

outputs of these circuits are only valid during a particular

phase of the power clock cycle. Hence, multiple-phase

clocking is required to drive a chain of cascaded adiabatic

logic circuits. The need for a multiple-phase power clock

not only increases the power dissipation of the clocking

network, but also it results in extra complexity of both the

logic and the required power clock generator. The 2N-2P

and the 2N-ZN2P circuits[2], and the efficient charge

recovery logic circuit(EClZL)[3] require four-phase

clocking. The pass-transistor adiabatic logic(PAL)E4]

requires two-phase clocking, which eliminates the path to

ground and thereby achieves higher power saving.

However, the floating low output will affect the circuit

performance. The PAL-2N circuit[5] uses two minimized

pull down...